In this tutorial I will use Verilog with  classical FPGA design. I bought perfect modern FPGA board ZYBO (ZYnq BOard) based on Xilinx Z-7010 from Digilent but latest tools from Xilinx VIVADO 2015.2 more focused on AP SoC programming while I want to just pure FPGA design without any linuxes bootloaders etc. So I wrote this tutorial to help people like me 🙂

In this example we make simple scheme: 2 signals IN and 4 OUT.

Vivado 2015.2 under Windows 7 64 bit was used with 16 GB of RAM.

Before using Zybo with Vivado you should add Zybo Definitions File to Vivado.

1. Good source for Board Definition files is Zynqbook website.Download The_Zynq_Book_Tutorial_Sources_Aug15.zip

2. Copy zybo folder with content from Archive path \sources\zybo\setup\board_part into D:\Xilinx\Vivado\2015.2\data\boards\board_files (if D:\Xilinx\Vivado\2015.2 is my PC you probably have C:\Xilinx etc…)

3. In board_files you should see other boards. Now our Zybo known by Vivado.

4. Download  ZYBO_Master.xdc from Digilent website unpack constraints files on local hard disk for example on Desktop.

I have latest Vivado Design Edition from Xilinx which comes with Digilent Zybo board.

Launch your Vivado.

Click Next

Set project name to gates2,

Keep rest settings unchanged unless you know what you doing.

Keep default RTL(Register Transfer Level) project, Press Next

In this tutorial we decided to use Verilog language so make sure it set correctly. Simulator language you can keep unchanged.

Click on “+” – Select – Create File.

Set Filename to gates2. Keep the rest unchaged. Press OK. Press Next.

Click Next.

Click “+”, Add Files.

Click on boards and select Zybo. If you still don’t have it follow steps in Preconditions: Adding Zybo board to Vivado.

If you don’t see ZYBO goto Preconditions Step.

Next.

Finish

Project files generated and ready for your design.

We will implement 2 input gates and 4 output basic gates and, or,  xor and  nor.

Click on Source file in Project Manager>Sources>Design Sources – Source code on Right-hand side should appear.

Modify Verilog file – add lines as highlighted below.

wire a,b;
reg [3:0]z;
always @(a or b)
begin
z[0] = a & b;
z[1] = a | b;
z[2] = a ^ b;
z[3] = !(a | b);
end

Rightclick on Design Sources and select Add Sources.

1. Add or create design souces.

2. “+” > Create File

Select xdc file from Sources>Constraints

At Synthesis phase we convert our circuit from register transfer level (RTL) into  a design implementation in terms of logic gates.

In Flow Navigator on Lefthand side.:

Next steps can be Simulation>Run Simulation or RTL Analysis>Schematic but we skip them in this tutorial and come directly to Synthesis>Run Synthesis.

Pay attention to jumpers.

JP7 – It should set to USB.

JP5 can be JTAG or QSPI

Connect ZYBO to PC with Micro-USB cable.

Photo taken from http://marsee101.blog19.fc2.com/blog-entry-2745.html

1. http://www.slideshare.net/MaryalaSrinivas/verilog-tutorial

2. http://www.instructables.com/id/Learn-Verilog-A-Brief-Tutorial-Series-on-FPGA-Desi/?ALLSTEPS

3. The ZYNQ BOOK – Make sure you download not only book archive but also tutorials book with sources.

4. HDL Chip Design- A Practical Guide for Designing, Synthesizing and Simulating ASICs and FPGAs Using VHDL or Verilog. By Douglas J. Smith

5. ZYBO Reference Manual

1. Project Archive

2. ZYBO Board Definition File.

3. ZYBO Master xdc file.

boris@borisivanov.com